This invention relates to programmable logic device integrated circuits, and more particularly, to programmable logic devices with memory decoder circuitry that may be adjusted to optimize timing constraints.
Programmable logic devices are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design (CAD) tools to design a custom logic circuit. These tools help the designer to implement the custom logic circuit using the resources available on a given programmable logic device. When the design process is complete, the CAD tools generate configuration data files. The configuration data is loaded into programmable logic devices to configure them to perform the desired custom logic function.
Programmable logic devices generally contain programmable memory elements into which the configuration data is loaded during device programming. With one suitable arrangement, programmable memory elements are implemented using volatile memory elements. These memory elements are often referred to as configuration random-access memory (CRAM). Once loaded, each CRAM cell produces a static output signal that controls a transistor or other electronic component in a region of programmable logic.
Programmable logic devices also generally contain blocks or regions of random-access memory (RAM). These memory blocks, which are sometimes referred to as embedded array blocks (EABs) are used to handle the storage needs of the circuitry on the device. During normal operation of a programmable logic device, the hardwired and programmable circuitry of the device performs read and write operations on the memory of the blocks. Memory blocks on a programmable logic device typically range in size from a few kilobits to about a megabit or more.
Data can be written to and read from an array of RAM cells in a memory block using bit lines. The array of memory cells in each memory block is addressed using an address decoder. Each address decoder receives address signals and coverts them into word line signals for addressing the memory cells in the array.
To allow sufficient time for the memory circuitry on a programmable logic device to operate properly, logic designers must ensure that their design satisfies certain timing constraints. For example, a logic designer must ensure that setup time (Tsu) and clock-to-output time (Tco) constraints are satisfied by the design. If these constraints are violated, the programmable logic device may not function satisfactorily.
The timing characteristics of conventional memory decoders are fixed, which can adversely affect the performance of certain logic designs. For example, a logic designer may only be able to satisfy certain setup time and clock-to-output time constraints in the programmable logic device by reducing the frequency at which the programmable logic device is allowed to operate in a system. Such compromises may not always be acceptable to the designer.
It would therefore be desirable to be able to adjust timing characteristics in the memory decoder circuitry of a programmable logic device so that a logic designer can improve circuit performance.